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RLR07C1800GSB14 Features:
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| The RLR07C1800GSB14/RLR07C1800GSB14E single RS-232 transmitters in a SOT23-6 package are for space- and cost-con- strained applications requiring minimal RS-232 commu- nications. These devices consume only 200µA of supply current from 7.5V to 12V supplies. The RLR07C1800GSB14/RLR07C1800GSB14E transmitter outputs are RS-232 compatible when powered from 6V to 7.5V supplies. They feature a shutdown input that reduces current consumption to only 1µA and forces the transmitter out- put into a high-impedance state. RS-232-compliant data transmission is guaranteed up to 460kbps. The RLR07C1800GSB14/RLR07C1800GSB14E are EIA/TIA-232 transmitters that convert CMOS/TTL logic levels to RS-232-compliant signals. The RLR07C1800GSB14E transmitter output is protected to 15kV per the Human Body Model, 8kV per IEC 1000-4-2 Contact Discharge, and 15kV per IEC 1000- 4-2 Air-Gap Discharge, providing protection against harsh environments. The RLR07C1800GSB14/ RLR07C1800GSB14E trans- mitters have a standard inverting output. |
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RLR07C1800GSB14 (Absolute) Maximum Ratings:
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| The MC100ES6039 is a low skew 2/4, 4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple ES6039s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one ES6039, the MR pin need not be exercised as the internal divider design ensures synchronization between the 2/4 and the 4/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. The 100ES Series contains temperature compensation. |
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RLR07C1800GSB14 Pinout:
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| belonging to Dolby Laboratories. Licenses to use this product must be acquired from Dolby Laboratories. 2. Use of this product in MPEG2-related products requires patent licenses from the following company. MPEG LA, LLC 250 Steel Street, Denver, Colorado USA 80206 |
| The device contains two types of internal memory - data memory and connection memory. There are four modes of operation - Connection Mode, Message Mode, BER mode and high impedance mode. In Connection Mode, the contents of the connection memory define, for each output stream and channel, the source stream and channel (the actual data to be output is stored in the data memory). In Message Mode, the connection memory is used for the storage of microprocessor data. Using Zarlink's Message Mode capability, microprocessor data can be broadcast to the data output streams on a per-channel basis. This feature is useful for transferring control and status information for external circuits or other TDM devices. In BER mode the output channel data is replaced with a pseudorandom bit sequence (PRBS) from one of 32 PRBS generators that generates a 215-1 pattern. On the input side channels can be routed to one of 32 bit error detectors. In high impedance mode the selected output channel can be put into a high impedance state. |
