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RLR07C1401FS Features:
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| The RLR07C1401FS is a quad differential line driver designed for digital data transmission over balanced lines. The RLR07C1401FS meets all the requirements of EIA Standard RS-422 and Federal Standard 1020. It is designed to provide unipolar dif- ferential drive to twisted-pair or parallel-wire transmission lines. The RLR07C1401FS offers improved performance due to the use of state-of-the-art L-FAST bipolar technology. The L-FAST technology allows for higher speeds and lower currents by utilizing extremely short gate delay times. Thus, the RLR07C1401FS features lower power, extended temperature range, and improved specifications. |
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RLR07C1401FS (Absolute) Maximum Ratings:
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| The RLR07C1401FS is a timing controller that combines an LVDS single pixel input interface with Nationals Reduced Swing Differential Signaling (RSDS™) output driver interface for (SVGA) XGA and Wide XGA resolutions. It resides on the TFT-LCD panel and provides the data buffering and control signal generation for (SVGA) XGA, and Wide XGA graphic modes. The RSDS™ path to the column driver contributes toward lowering radiated EMI and reducing system dynamic power consumption. This single RSDS™ bus conveys the 8-bit color data for (SVGA) XGA, and Wide XGA panels at 170 Mb/s when using VESA 60 Hz standard timing. |
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RLR07C1401FS Pinout:
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| 12 Bit Resolution 1.3 GS/s Sampling Rate 4:1 Input Multiplexer Master-Slave Operation for Synchronous Operation of Multiple Devices Differential Analog Output Input code format: Offset Binary Output Swing: 600 mV with 50 Ω Termination 3.3V NMOS-Compatible Data Inputs Differential ECL or Sinusoidal Clock Input LVDS Compatible Clock Output 10-bit static linearity Reference Output/Input Pin for Accurate Full-Scale Adjustment. 3.3V and -5.2V Power Supply 77 Lead HSD package |
| Strap:see Note 4 Notes: 1. DQ-to-I/O wiring may be changed within a byte 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ/DQS resistors should be 22 Ohms. 4. VDDID strap connections(for memory device VDD, VDDQ); Strap out :(open) : VDD=VDDQ Strap In (Vss) : VDD=VDDQ 5. SDRAM placement alternates btw the back and front sides for the DIMM 6. Address and control resistors should be 22 Ohms |
