|
RLR07C1300GS Features:
|
| S0 and S1 are used to program the frequency range and bandwidth of the modulated output clocks SSCLK1a/b and SSCLK2. S0 and S1 of the RLR07C1300GS are designed to sense three different analog levels. With this tri-level structure, the RLR07C1300GS is able to detect 9 different logic states. Refer to tables 5, 6 and 7 for the results of each of these 9 states. The level of each state is defined as follows: |
|
RLR07C1300GS (Absolute) Maximum Ratings:
|
| Warnhinweise Bauelemente können aufgrund techni- scher Erfordernisse Gefahrstoffe enthal- ten. Ausknfte darber bitten wir unter An- gabe des betreffenden Typs ebenfalls ber den Vertrieb Infineon Technologies einzu- holen. Infineon Technologies Bauelemente drfen nur mit ausdrcklicher schriftlicher Geneh- migung von Infineon Technologies in le- benserhaltenden Geräten oder Systemen eingesetzt werden, falls beim Ausfall des Bauelementes berechtigter Grund zur An- nahme besteht, daß das lebenserhaltende Gerät oder System ausfällt bzw. dessen Si- cherheit oder Wirksamkeit beeinträchtigt wird. Lebenserhaltende Geräte und Syste- me sind zur chirurgischen Einpflanzung in den menschlichen Körper gedacht oder untersttzen bzw. erhalten das menschli- che Leben. Sollten sie ausfallen, besteht berechtigter Grund zur Annahme, daß die Gesundheit des Anwenders gefährdet wer- den kann. |
|
RLR07C1300GS Pinout:
|
| Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP7311 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP7311 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for todays Internet appliances. |
| One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL One of two latched inputs that select the HOST and MREF output frequency One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL One of two latched inputs that select the HOST and MREF output frequency Four 3.3V 66.67MHz clock outputs, generated from the spread spectrum PLL Host clock pair #1; one of six pairs of current-steering differential current-mode outputs. The current is established via a reference current at IREF and a multiplying factor set by ISEL_0:1 |
| Port selection is accomplished on a first-come, first-serve basis. Whichever port comes out of reset first will obtain control. For the 3-wire port, this is done by bringing RST high. For the 1-Wire port, this is done on the first falling edge of I/O after the reset and presence pulses. (See 1-Wire Signaling section.) |
