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RLR07C1243FS Features:
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| The MRLR07C1243FS is a 1 Mbit (64Kb x16) non-vola- tile memory that can be read, erased and repro- grammed. These operations can be performed using a single 5V supply. On power-up the memo- ry defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are writ- ten to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The blocks in the memory are asymmetrically ar- ranged, see Table 2., Bottom Boot Block Address- es, MRLR07C1243FS. The first 32 Kwords have been divided into four additional blocks. The 8 Kword Boot Block can be used for small initialization code to start the microprocessor, the two 4 Kword Pa- rameter Blocks can be used for parameter storage and the remaining 16 Kwords are a small Main Block where the application may be stored. Chip Enable, Output Enable and Write Enable sig- nals control the bus operation of the memory. They allow simple connection to most micropro- cessors, often without additional logic. The memory is offered in PLCC44 and TSOP40 (10 x 14mm) packages. In addition to the standard version, the packages are also available in Lead- free version, in compliance with JEDEC Std J- STD-020B, the ST ECOPACK 7191395 Specifica- tion, and the RoHS (Restriction of Hazardous Sub- stances) directive. All packages are compliant with Lead-free soldering processes. The memory is supplied with all the bits erased (set to 1). |
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RLR07C1243FS (Absolute) Maximum Ratings:
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| † Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. |
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RLR07C1243FS Pinout:
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| Hardware Reset, active Low. Provides a hardware method of resetting the HY 29F800 to the read array state. When the device is reset, it immediately terminates any operation in progress. The data bus is tri-stated and all read/write commands are ignored while the input is asserted. While RESET# is asserted, the device will be in the Standby mode. |
| The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven Low, the configuration device resets its address counter and tri-states its DATA pin. The CE pin also controls the out- put of the AT17F Series Configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subse- quently driven High, the counter and the DATA output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE. |
