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00041275.80GT9F0006 Features:
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| Each independent transceiver channel in 00041275.80GT9F0006 is capable of operating at 2.488-3.1875Gbps at full-rate, and 1.244-1.59375Gbps at half-rate. The four on-chip transceivers shown in Figure 1-2 can also be configured as a single 10 Gigabit Attachment Unit Interface (XAUI), for both 10G Ethernet and 10G Fiber Channel or proprietary backplane interfaces, providing up to 12.75Gbps of data throughput at full duplex. The 00041275.80GT9F0006 also supports the 10 Gigabit Media Independent Interface (XGMII) on the parallel interfaces. The device can be used as an XGMII Extended Sublayer (XGXS) device to support longer PCB traces between optical transceiver modules and switch fabrics, as shown in Figure 1-1. |
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00041275.80GT9F0006 (Absolute) Maximum Ratings:
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| Figure 1 shows a typical application circuit for the 00041275.80GT9F0006 MMIC. The device is internally matched to 50 Ω, and therefore does not need any external matching. The value of the input and output DC blocking capacitors C2 and C3 should not be more than 100 pF for applications above 100 MHz. However, when the device is operated below 100 MHz, the capacitor value should be increased. |
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00041275.80GT9F0006 Pinout:
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| General purpose pin 4 General purpose pin 3 Reset input 1: self-powered. 0: bus-powered Keyboard matrix sense input 1 Keyboard matrix sense input 2 Keyboard matrix sense input 3 Keyboard matrix sense input 4 Keyboard matrix sense input 5 Keyboard matrix sense input 6 Keyboard matrix sense input 7 Keyboard matrix sense input 8 Power enable for downstream port 1 Power enable for downstream port 2 Over current flag for downstream port1 Over current flag for downstream port2 Ceramic resonator or crystal out Ceramic resonator or crystal in |
| RESET/Output Enable input (when SER_EN is High). A Low level on both the CE and RESET/OE inputs enables the data output driver. A High level on RESET/OE resets both the address and bit counters. The logic polarity of this input is programmable as either RESET/OE or RESET/OE. This document describes the pin as RESET/OE. |
| The MX98715A controller is an IEEE802.3u compliant single chip 32-bit full duplex, 10/100Mbps highly inte- grated Fast Ethernet combo solution, designed to ad- dress high performance local area networking (LAN) system application requirements. |
