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0.5W27V Features:
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| RON t 4 W Typical Less Than 0.25 ns−Max Delay Through Switch Nearly Zero Standby Current No Circuit Bounce Control Inputs are TTL/CMOS Compatible Pin−For−Pin Compatible With QS3400, FST3400, CBT3400 All Popular Packages: SOIC−24, TSSOP−24, QSOP−24 All Devices in Package TSSOP are Inherently Pb−Free* |
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0.5W27V (Absolute) Maximum Ratings:
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| The CY7C107B and CY7C1007B are high-performance CMOS static RAMs organized as 1,048,576 words by 1 bit. Easy memory expansion is provided by an active LOW Chip Enable (CE) and three-state drivers. These devices have an automatic power-down feature that reduces power consump- tion by more than 65% when deselected. |
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0.5W27V Pinout:
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| The deserializer stays in lock until it cannot detect the same data boundary (stop/start bits) for four consecutive cycles. Then the deserializer goes out of lock and hunts for the new data boundary (stop/start bits). In the event of loss of synchronization, the LOCK pin output goes high and the outputs (including RCLK) enter a high-impedance state. The users system should monitor the LOCK pin in order to detect a loss of synchronization. Upon detection of loss of lock, sending sync patterns for resynchronization is desirable if reestablishing lock within a specific time is critical. However, the deserializer can lock to random data as previously noted. |
| • Same form, fit, and function as SSTL16877 • Full DDR 200/266 solution @ 2.5 V when used with PCKV857 • See SSTV16856 for driver/buffer version with mode select. • Available in TSSOP-48, TVSOP-48 and 56 ball VFBGA packages |
